FIG. 12 is a perspective view of a prior art loaded line phase shifter and FIG. 13 is an equivalent circuit diagram thereof. In the figures, reference numeral 120 designates a loaded line phase shifter. In the loaded line phase shifter 120, a main transmission line 3 one-quarter of a wavelength long is disposed on a semiconductor substrate 12 comprising silicon, GaAs, or the like. An input pad (input terminal) 1 and an output pad (output terminal) 2 are disposed at opposite ends of the main line 3. Loaded lines 4a and 4b are connected to the main line 3 in the vicinity of the input and output pads 1 and 2, respectively. Field effect transistors (hereinafter referred to as FETs) 5a and 5b are connected to ends of the loaded lines 4a and 4b, respectively. The FET 5a includes a drain 7, a source 9, and a gate 8, and the FET 5b includes a drain 10, a source 9, and a gate 11. The source 9 is common to the FETs 5a and 5b, through which the FETs 5a and 5b are grounded. Gate bias pads (gate bias terminals) 6a and 6b are connected to the gates 8 and 11, respectively. The common source 9 is grounded by a wire 13 comprising gold or the like.
FIG. 14 is an equivalent circuit diagram of the loaded line phase shifter of FIG. 12, in which the FETs 5a and 5b are included in the loaded lines 4a and 4b. In FIG. 14, Zc is characteristic impedance of the main line 3, .theta. is electrical length of the main line 3, Yi is admittance of a loaded line 4a' (4b') including the loaded line 4a (4b) and the FET 5a (5b), and Zo is characteristic impedance of the whole phase shifter.
A description is given of the operation.
In a circuit shown in FIG. 15, it is supposed that impedances when the circuit is viewed from the input and output terminals are equal to impedances when the input and output terminal are viewed from the circuit and the transmission quantity is equal to .phi.. Such a circuit can be represented by a K matrix. A plurality of such circuits can be connected in cascade.
In order to represent the loaded line phase shifter shown in FIG. 13 by a K matrix, admittance Yi of the load including the loaded line 4a (4b) and the FET 5a (5b) is represented in a K matrix as follows: ##EQU1##
Meanwhile, characteristic impedance of the main line 3 is represented in a K matrix as follows: ##EQU2##
Therefore, the whole loaded line phase shifter is represented in K matrix as follows: ##EQU3##
Since the admittance Y is represented by conductance G and susceptance B, the admittance Yi of the load including the loaded line 4a (4b) and the FET 5a (5b) is represented as follows: EQU Yi=Gi+jBi (4)
When the equation (4) is substituted for the equation (3), respective components A, B, C, and D of the K matrix are represented as follows: EQU A=D=cos .theta.-Bi Zc sin .theta.+jZc Gi sin .theta. (5) EQU B=jZc sin .theta. (6) EQU C=2G1(cos .theta.-Bi Zc sin .theta.)+jZc(2Bi Yc cos .theta.+Yc.sup.2 +Gi.sup.2 -Bi.sup.2) sin .theta. (74)
When this K matrix is converted to S parameters, since the loaded line phase shifter shown by the equivalent circuit of FIG. 13 is a symmetrical circuit, the following equations (8) and (9) are obtained. ##EQU4## where Yo is admittance and Zo is impedance.
When it is supposed that the loaded line phase shifter shown in FIG. 13 has no reflection and no loss, the above-described S11, S21, and Gi are represented as follows: EQU S11= 0 (10) EQU .vertline.S21.vertline.= 1 (11) EQU Gi=0 (12)
When the equation (10) is combined, the equation (8) is converted to EQU BYo=CZo (13)
When the equations (5), (6), (7), (8), and (12) are substituted, the equation (9) is converted to ##EQU5##
When the equation (14) is multiplied by its conjugate formula, the following equation is obtained. EQU S12=S21= cos .theta.-Bi Zc sin .theta.-jZc Yo sin .theta. (15)
When the transmission quantity of this phase shifter is .phi., the following equations are obtained from the above equation (15). EQU cos .phi.=cos .theta.-Bi Zc sin .theta. (16) EQU sin .phi.=jZc Yo sin .theta. (17)
Since the main line 3 is one-quarter wavelength long, i.e., .theta. is 90.degree. and reflected waves at the input and output ends cancel each other, so the equations (16) and (17) are respectively reduced to EQU cos .phi.=-Bi Zc (18) EQU sin .phi.=-jZc Yo (19)
and the transmission quantity .phi. is represented as follows: EQU .phi.=cos.sup.-1 (-Bi Zc) (20)
FIGS. 16(a) and 16(b) are equivalent circuit diagrams of the loaded line phase shifter of FIG. 12 illustrating states before and after the phase of the phase shifter is shifted, respectively FIG. 16(a) shows a state where the FETs 5a and 5b are turned on and FIG. 16(b) shows a state where the FETs 5a and 5b are turned off.
When the impedance and the electrical length of the loaded line 3 are ZL and .theta.L, respectively, and the off-capacitance of the FET is C, the susceptance component B1 of the loaded line 3 in the state of FIG. 16(a) is represented by EQU B1=-1/ZL tan .theta.L (21)
and susceptance component B2 of the loaded line 3 in the state of FIG. 16(b) is represented by ##EQU6## where .omega. is angular frequency.
Generally, signals traveling through a phase shifter are represented by vectors as shown in FIG. 17, and signals traveling through the phase shifter in the states of FIGS. 16(a) and 16(b) correspond to vectors OD and OE of FIG. 17, respectively. Therefore, the following equation (23) is obtained from FIG. 17 and the equations (18) and (19), and the following equations (24) and (25) are obtained from the equations (23), (21), and (22). ##EQU7##
As described above, in the conventional loaded line phase shifter shown in FIGS. 12 and 13, values of Zc, L, and C are obtained from the equations (18), (19), (21), and (22).
In the conventional loaded line phase shifter thus constituted, the reactance L of the loaded line, the off-capacitance C of the FET, and the characteristic impedance Zc of the main line are controlled to attain a desired phase shift quantity.
However, in the structure of the conventional loaded line phase shifter comprising a main line, two loaded lines connected to opposite ends of the main line, and two source-grounded FETs connected to the loaded lines, however, only one phase shift quantity is determined. When a two-bit phase shifter is desired, two phase shifters having different phase shift quantities should be connected in cascade, increasing the size of the whole phase shifter.
Meanwhile, the inventor of the present invention proposed an improved loaded line phase shifter in Japanese Published Patent Application No. 3-70201 which corresponds to U.S. Pat. No. 5,032,806, in which two loaded lines are connected to opposite ends of a main line, a source electrode and a drain electrode of an FET are respectively connected to positions spaced from the nodes of the loaded lines and the main line by the same electrical length, and a bias circuit comprising a stripline for controlling a bias voltage is connected to a gate electrode of the FET. In this phase shifter, since susceptance values of two loaded lines are controlled by one FET and it is not necessary to ground the source electrode, the degree of freedom in pattern design is increased. However, as in the conventional loaded line phase shifter shown in FIG. 12, since only one phase shift quantity is obtained by one phase shifter, two phase shifters have to be connected together to make a two-bit phase shifter.